Logical binary powering circuits



June 16, 1959 J R. LOGAN LOGICAL BINARY POWERING CIRCUITS 3 Sheets-Sheet 1 Filed Oct. 8, 1956 June Filed 00T..

OrO-1 5 .Sheets-Sheet 2 t ga a [afl c -G u d 1 0 l O 0 b C' Gd FIG. 2.

O O bc bd l be l ce A IN VEN TOR.

J. Robert Logon ZM F7@ Y AGENT June 16, 1959 J R. LOGAN LOGICAL BINARY PCWERING CIRCUITS 3 Sheets-Sheet 5 Filed Oct. 8, 1956 INVENTOR.

J. Rober? Logon hn-lr United States Patent O LOGICAL BINARY PWERING 'CIRCUITS J Robert Logan, Norristown, Pa., assignor to Sperry Rand Corporation, New York, N.Y., a corporation of Delaware Application ctober 8, 1956, Serial No. 614,633

Z2 |Claims. (Cl. 235164) The present invention relates to computation circuits,

particularly of the type operating in the binary system` of notation, and is primarily concerned with improved circuits of simplified construction for rapidly deriving the binary power, such as the binary square or binary cube, of any binary number. The present invention is further concerned with achieving such binary powers, such as squares and cubes, through the `utilization of simpler circuits than those suggested heretofore.

In various logical computations, it is often required that a number be raised to a power thereof, and in practice, it has been found that by far the most frequent of such computations involves the taking of the square (and, somewhat less frequently, the cube) of a number. Prior computation systems have, for the most part, derived such squares or cubes through a process of `successive additions of the number itself whereby the taking of a square or cube has often consumed a relatively long time, particularly when the number squared comprises a large` number of binary digits.

' In an effort to avoid this clear disadvantage of prior squaring or cubing circuits, attempts have been made to produce various logical networks adapted to accept a binary number and thereafter to produce a desired power thereof, but such prior circuits have, for the most part, been extremely complex, thereby raising serious questions of possible failure. The present invention serves to obviate the foregoing difculties, and relates to logical networks adapted to effect a binary power of an input number with fewer additions and in a more simple overall circuit than has been the case heretofore.

Another object of the present invention resides in the provision of binary squaring and cubing circuits comprising a plurality of registers interconnected to accept various factors of a mathematical squaring or cubing process whereby signals in the said registers may be added to produce a desired binary square or cube. In this respect, the present invention is further concerned with such circuits wherein the number of registers employed is reduced to a minimum, and wherein further, the number of additions required is similarly reduced to a minimum.

A still further object of the present invention resides in the provision of improved logical networks adapted electrically to collapse the number of register stages required for a binary power-taking process, thereby to effect a more efficient utilization of storage registers during such a process.

Another object ofthe present` invention ,resides in the provision of logical binary squaring circuits in particular, and binary power-taking circuits in general, which are simpler in construction, more efficient in operation, and less subject toioperating failures than has been the case heretofore.

In providing for the foregoing objects and advantages, the present invention contemplates the provision of binary squaring and cubing circuits comprising an input register or a plurality of input lines adapted to receive signals representative of the digits of a binary number `which is to be raised to a desired power thereof. The said signals may, in accordance with the present invention, be gated to accumulator means in accordance with mathematical factors of a squared or cubed number, and this gating process is such that the several factors are automatically disposed in appropriate stages or orders of the said accumulator means, in accordance with the Various powers of said factors.

In a preferred embodiment of the present invention, the accumulator means may comprise a plurality of intermediate storage registers whereby signals in the aforementioned input register or input 'lines are gated simultaneously to appropriate stages of the said intermediate storage registers. Such a register arrangement is further associated with a parallel adder adapted thereafter to receive, in sequence, the factor representing signals in the several intermediate storage registers whereby the said parallel adder produces, at its output, a binary train directly representative of the desired power of the binary number originally placed in the aforementioned input register.

When this particular form of the invention is employed, the intermediate registers may be collapsed thereby to effect a more efcient utilization of register stages, whereby a minimum number of intermediate storage registers is required; and in addition, this collapsing technique permits the desired binary power to be` effected with a minimum number of parallel additions,

thereby increasing the operating speed of the overall circuit. The aforementioned register collapsing is effected, in accordance with the present invention, through the use of improved logical networks which electrically take into account possible binary digits which can occur in various locations of the overall system under any circumstances; and the said logical networks, to be described, in fact may be employed in power-taking circuits adapted to accept binary numbers having any arbitrary number of digits without any increase in com-f plexity of the said collapsing logical networks.

As will become apparent from the subsequent description, the present invention is in fact adapted to effect the binary square of any input binary number having N digits, where N may be either an even or an odd number; and when the register and parallel adder embodiment of the present invention is employed, the circuit can effect the desired binary square through the utilization of K storage registers, where `K equals l-ZY K equals cubing circuits and, in fact, by appropriate application of my invention and of the techniques to be described, circuits adapted to tale any binary power (and for that matter, any ternary or other baseipower)v may bereadily derived.

The foregoing objects, advantages, construction and operation of the present invention will become more readily apparent from the following description and accompanying drawings, in which:

Figure 1 is a logical Idiagram of one form of binary Before proceeding with a detailed description and analysis of the several representative circuits described above, various delinitions of notation to be employed should be recognized. As wlll become apparent from the following description, any number can be represented mathematically by a succession of letters such as abcde, and when such an arbitrary number is meant to denote a binary number, the several letters a, b, c, etc., each comprise either a l or a 0. When an input register or a plurality of input lines is adapted to receive such a number, the various digits a, b, c, etc., will ordinarily be disposed in separate stages of the said input register or on separate input lines. As will also be described, the binary `digits in such an input register may, in, accordance with the present invention, be gated to various register stages, in accordance withV logic to be discussed; and the gating technique may utilize means responsive to the presence of a l, or of a in various stages of the input register. For the most part, during the subsequentdiscussion (in fact during the entire subsequent discussion except for the representation of digits in the input register), an unbarred letter representation, for example b, represents a binary l in the b place or orderr of a given register; while a barred letter, for example b, is meant to` represent a binary 0 in the said b place or order.

Moreover, as will become apparent from the following description, the gating networks of the present invention are adapted, under some circumstances, to logically combine digits in various orders of the input register; and in this respect therefore, a designation such as ab, at the output of a gate, is meant to represent a condition wherein the said gate produces a l output only when two coincident "1s from the a and b orders are applied to the input of the said gate. Similarly, a designationsuch as ab at the output'of a gate, is meant to represent a condition wherein the said gate produces a l output when the a input thereto is a lfand the b input thereto is a 0 (i.e. b). j v

Having recognized the foregoing definitions which are adopted merely for simplicity of explanation, let us now examine the logic, and circuits utilizing such logic, for eecting a desired binary square in accordance with the present invention. It should first be noted that any binary number (abcd)2 may be expressed, to the base 2, as:

In determining the square of such a number, the accepted mathematical procedure is to square the individual digits, and to add thereto twice the crosspro'ducts of the several digits. Such a squaring procedure yields the following factors:

Square of digits: c222; 62.22; 02.22; d2

. 4 In the binary system, the digits a, b, c, and d will be, of course, either l or 0. Therefore, in such a binary system, a2=a; b2=b; `c2=cg and d2=d.

The individual steps involved in the squaring process of an arbitrary number (abcd) may accordingly be set up, as to powers, in a first truth` table, as follows:

a 0 b 0 c 0 d ab ac ad 0 0 0 O 0 0 bc bd 0 0 0 0 0 0 0 cd 0 0 second table appears as follows:

' ing the said table.

Reglsterl a 0 b 0 c 0 d RegisterZ ab ac d bd cd 0 0l If each of the horizontal rows in the above second: table (2) is considered to comprise the stages of a sep-v arate storage register, or is considered to comprise a; `distinct parallel input to an accumulator, it will be noted' that, except for the factor bc, the squaring of a four-V digit number (abcd) could be accomplished with only; two storage registers and/or with but a single parallel addition. This desirableresult (i.e. the reduced number` of registers and/ or addition steps) can actually be accom-y plished by logically combining the factors b and bc in; the 24 column of the above table, thereby further collaps- This logical combination may be eifected, for instance through the use of coincident and,l inhibition type gates, by recognizing the following with, respect to the factors b and bc:

b will always be l or O; bc willalways be l or 0;

b bc Sum Carry Oase 1 0 0 0V .0 (c can be 0 or 1) Case 2 1 0 1 0' (c must be O) Case 3----'. 1 1 0 1 (c must be 1) In cases 1 and 2, there is no carry (i.e. a carry of"f0)' whereby the factors b and bc can readily Ybe logically combined, for example by utilizing the said factors as separate inputs to a coincidence gate. The only possible problem in such a logical combining arrangement arises in case 3 when both b and bc are 1s, for then a of 1. must be taken into account. This carri,r situation may be readily taken into consideration, however, by` logically combining, or adding the` factors band bc, and by thereafter buing any resultant carry to the next higher order or stage in the irst register or accumulator'comf prising the logical squaring circuit of the present inven# tion; for, referring to the .second truth table (2) given above, it will be noted that, in the absencevof a carry, such a next Yhigher register stage always contains a O (see the 25 stage in the rst register representation of the second .truth table, above). In particular, it should be noted that the sum above can always be repre-` sented bythe factor yb5 (where E equals 0 as opposed to c which represents a l), and the carry above can always be represented by bc.

Thus, the factors b and bc can readily be logically combined thereby to effect the desired collapse of the truth table to a minimum number of registers and/or addition steps in an accumulator, and this logical combining takes into account any carry which might be generated. It should be noted that the carry discussed above is in fact the only -carry which need be considered `and, moreover, this carry will never be propagated beyond the aforementioned next higher order or stage in a preselected register or accumulator.

A typical example of a logical squaring circuit adapted to provide the square of a number (abcd) could therefore comprise a rst register adapted to store or set up, in ualternate locations, the factors a., b, c, and d, with the b Istage of this first register including a half adder or other logical network 4responsive to the relative states of the digits b and c and adapted, selectively, to insert a carry into the stage` between those storing the factors a and b; a second register, adapted to store or set up, in appropriate stages thereof, the factors ab, ac, ad, bd, and cd; and a parallel adder adapted to sum the numbers contained in the said registers, the said summation comprising the desired square. In place of the aforementioned half adder, the logical combining circuit may comprise a circuit responsive to the factors b and c (Le. b and bc), and adapted to provide the desired combining of factors by inserting bi: ina preselected register order, and the factor bc in the next higher order. Such circuits will in fact be described subsequently.

It will be appreciated that the foregoing techniques and structures need not be confined to a four-digit number abcd, and analogous considerations and structure may be employed, as has been mentioned previously, in effecting the square of any binary number having N digits. The component bits of an input register containing such an N digit number may, in accordance with the techniques described, be gated into K accumulators or 'storage registers where N K-r when N is an even number, and

N- l K 2 when N `is an odd number, and, as has also been discussed, the digits in the said `K accumulators or storage registers may then be combined into the desired binary square by K-l parallel additions; e.g. when N equals either 14 or 15, seven registers and six additions are required; when N equals 6 or 7, three registers and two additions are required, etc. It will further be appreciated, of course, that intermediate storage registers may, if desired, be dispensed with whereby, through the use of an appropriate gating network, the several binary factors discussed above may be gated, at properly spaced times, from a plurality `of input lines or from an input register to the several inputs of a parallel adder, whereby as before the sum output of the said parallel adder provides the desired square of the number in the said input register. The use of intermediate storage registers, however, comprises a preferred embodiment of the present invention due to the simplified gating and timing which results from such use.

One binary squaring circuit constructed in accordance 'with the previous ldiscussion and adapted to eiect the "binary square of Va four-digit binary number, is illustrated in Figure 1. Thus, referring to Figure l, it will be seen that in accordance with the present invention, an input register 10, comprising four stages, 11 through 14 inclusive, may be adapted to receive, 4on separate input lines thereto, the several binary digits a, b, c, and d, representing an input binary number to be squared. The several register stages 11 through 14 may in fact comprise flip-flops or single-step binary counters, and are purely conventional in configuration. Moreover, the several gates, to be described, are similarly of conventional configuration, as are the parallel adders utilized in the several embodiments of the invention. Typical components which may be utilized in the several circuits of the present invention are in -fact described inhtext High Speed Computing Devices by the stati of Engineering Research Associates, 1950, McGraw-Hill Book Company, Inc.

Returning now to Figure l, it will be seen that th'e binary squaring circuit further includes a pair of intermediate storage registers 15 and 16, and each of these registers comprises seven stages. Register 15 is adapted to receive the biliary numbers a, c, and d, while register 16 is adapted to receive the binary numbers ab, ac, ad, bd, and `cd; and the combined factors so placed in intermediate register 16 are inserted therein through the provision of a coincidence gating network comprising `a plurality of gates 17 through Z1 inclusive. It will be noted, for instance, that gate 17 has two inputs thereto derived respectively from the l output terminals of input register stages 1l. and 12, whereby a l is inserted into the ab position of register 16 only when the a and b positions 11 and 12 of input register 10 contain 1s. A similar analysis applies to the ac, ad and bd positions of the said intermediate register 16.

It will be appreciated from an examination of the symbols in the register stages of registers 15 and 16 that the factors inserted into the several stages correspond essentially to the collapsed second table (2) given previously, except for the second and third stages of intermediate register 15. Moreover, it will be noted that the registers iii and id include dummy stages which always have a binary 0 `therein and these latter stages again conform to the representation given previously with respect to the collapsed second table.

As has already been discussed, the normal factors present during the taking of a binary square would, in the absence of other considerations, require an additional intermediate register and an additional addition step to take into account a single factor. Thus, referring 'to the second collapsed table (2), discussed above, it will be noted that in the absence of other considerations, an entire register would have to be utilized in the circuit of Figure l merely to accept the factor bc in the 24 position. ln order to reduce the number of stages required as well as the number of additions necessary, a further logical network comprising a 4gate 2t?. and a half adder 23 is employed. The gate 22 is of the coincidence type `and has two inputs supplied, via clock controlled gates 7b and 7c, from the 1 outputs of the b and c orders `l2 'and 13 of the input register 1), whereby the output of gate, 22 represents a logical combining of the factors b and c. The output of gate 22 may thus be employed as one input to half adder 23, while a second input thereto is derived, via clock controlled gate "i b, from the l output terminal of the b order 12 in input register 10. Half adder 23 again may be conventional in configuration and operates to provide a sum output on line 24 which is inserted into stage 25 of intermediate register 15, and the said half adder also acts to provide a carry output on line 26 which is inserted into stage 27 of intermediate register 15. This utilization of gate 22 and half adder 23, interconnected as illustrated, eliminates the necessity of a separate register for the bc factor, and further reduces by one the number of additions required.

lt should be noted that the carry appearing on line 26 and inserted into register stage 217, is inserted into a stage which would normally have a 0 therein (see the 25 representation of register 1 in the collapsed second table `(2) given previously). Therefore, any carry ins'erted into register stage 27 cannot under any circumstances be propagated beyond the said register stage 27, wherefore, the logical circuit illustrated in Figure 1 effects the desired ultimate collapse of the register in a most etlicient manner. lt will be appreciated, therefore, that the several stages of registers 15 and 16, disclosed in Figure 1, are adapted to receive respectively either an input digit, a logical combination of two input digits, or a signal representative of the relative states of two input digits; and these several digit signals are directly inserted into the various register stages at appropriate places corresponding to the order of the several factors.

In operation, means are normally supplied for initially clearing each of the stages in registers 1l), 15 and 16 to a state. An input number abcd is then inserted into input register 10, and the number so disposed in register is thereafter gated simultaneously, under control of a clock signal, to appropriate stages of the intermediate registers and 16. Subsequent to this initial gating step, the signals in registers 15 and 16 are gated out of the stages thereof, again under the control of a clock signal, into a conventional parallel adder 28 whereby the said adder 28 performs a single addition thereby to produce at its output a binary representation of the square of the number abcd.

It will be appreciated from the foregoing discussion that the particular circuit shown in Figure 1 includes gating means 7a-7d for transferring signals from register 10 to the registers 15 and 16 as well as further gating means Saz-8g and 9a-9g for transferring the temporarily stored signals out of intermediate registers 15 and 16 into parallel adder 28. These gating means are normally controlled by appropriate clock sources (see Figure 1) thereby to effect the necessary timing in the overall cir- .cuit operation. For purposes of sirnplicity, the parallel adder 28 has not been illustrated in detail in Figure l.

.An example of an adder suitable for use in the device of Figure 1 is illustrated and described in Arithmetic Operations in Digital Computers, by R. K. Richards, published by D. Van Nostrand Co., luc., New York, in 1955, page 83 et seq.

While the circuit shown in Figure 1 is particularly directed toward deriving the square of a four-digit number, it must be emphasized that the gating and combining logic inherent in the circuit of Figure l in fact applies directly to any binary number having N digits. It should further be noted that the circuit of Figure 1, comprising as it does an input register, intermediate register, a parallel adder, gating means, and timing sources, finds general application in deriving powers other than squares, and

la similar such circuit may be developed, in accordance with considerations `and techniques subsequently to be described, for deriving the binary cube, for instance, of a binary number. Moreover, the particular logical network lshown in Figure l, and utilized to effect final collapse of the overall register means, may be utilized in any squaring circuit wherein N is an even number, for, in this latter circuit, development of the binary factors will always -produce a single extra factor which should be combined with another factor in achieving the desired register collapse. The utilization of a gate such as 22 and a half adder such as 23 represents a somewhat more complex logical combining circuit than is actually necessary, how- ;ever, and a simpler circuit may in fact be employed for this portiongof the overall network. Such a simplified -circuit is illustrated in the arrangement of Figure 2 wherein the binary square of a six-digit number abcaef is derived.

Again, before proceeding with the description of the circuit shown in Figure 2, the logic of the said circuit will be more readily appreciated by considering the When the representation of the squared number' is cx? panded, as before, a further table can be derived, as follows:

21 2 2E 27 2 2s 24 2' 22 2x 2 wi attract a ac a ac a c c 0 0 bc bd b cc de 0 0 0 Examining the above table (4), it will be noted that except for the factor cd in the 2 column, the logical network could take the form of an input register feeding' three intermediate storage registers whereby the factors in the said intermediate storage registers could thereafter be summed in two parallel additions. This desirable situation can in fact be created by again producing further collapse of the table through a logical combining of the factors c and cd in the 26 column.

Examining these two factors c and cd, and notingithat when c equals 0, cd cannot equal 1, the following truth table may be derived:

c cd Sum Carry Referring now to the table (5), illustrating the relative states of the factors c and cd, it will be noted that the only time the sum of l occurs is when c equals l and cd equals 0 (i.e. d must, under these circumstances equal 0). This particular sum of 1 condition can always be represented as C22-,I i.e. a sum of 1 will be produced only when there is a 1 in the c place and a fO in the d place of the input register. Moreover, further examining the table (5), it will be noted that the only time a carry of 1 occurs is when c equals l and cd equals l (i.e. d must, under these circumstances equal 1). This latter carry of l situation can be represented as cd (i.e. before a carry of 1 occurs there must be binary ls in both thec and d places of the input register). Accordingly, thevfactor table given previously can be ultimately collapsed in the 27 and 28 columns thereby to eliminate the cd factor in the 26 column thereof; and this ultimate collapse may be depicted as follows, with respect to the said 27 and 26 columns:

cd ad ac af bd be Returning now to the circuit of Figure 2, it will be noted that except for the aforementioned considerations relating to the ultimate collapse of the register into a minimum number of register stages, the overall arrangement for effecting the binary square of a six-digit number, abcdef, is essentially the same as the arrangement given with respect to Figure 1 for deriving .the binary square of a four-digit number, abcd. In particular, the arrangement'of Figure 2 again employs an input register 30 comprising six stages adapted to receive respectively the several digits a through f, representing the input nurnber to be squared. The outputs of the severalstages in input register 30 can be gated, as before, into appropriate stagesof a first intermediate storage register 31, while variousl factors representing a logical combining of vpairs of digits in input register 30 can be gated respectively intogthe stages of second and third intermediate `storage vv.registers 32 and 33.

The factors so `gated into the stages `of registers 32 and 33 are `again passed :to `these -stages under `the control of -agating chain 34 disposed `between input register 30 and *the said 4second intermediate storage register 32, and 'under the `control `of `a further ,gating -chain 35 disposed between the said input register 30 and the said third intermediate storage register 33. For `ease of understanding, the several digits utilized as inputs to the gates in-chains V34 and 35 as well as the several factors appearing -in the stages yof registers 30 *through 33, have been fdesignated at appropriate locations in the logical repre- :sent-ation of Figure 2.

p `ln providing `for the ultimate register collapse dislcussed previously and in `place of the gate andhalf adder Aalready `described in reference to `Figure 1, a circuit compris'ing gates 36 and 37 is employed between input regis- -ter 30 and appropriate stages of the :lirst intermediate register 3'1. Gate 36 `comprises a coincidence gate Vhaving two inputs from the l output terminals `of the c "and d stages lin input register 30, whereby a t11 `is transferred via gate 36 into the stage 38 of storage register 31 only `when the c and d digits .areboth 1l Similarly, gate 37 is of the ycoincidence type and has its two inputs lderived, `respectively from the ""1 output terminal of the fr: :stage in `register `30, `and from the output "terminal tof the d :stage in register 30, -whereby the gate 37 trans- :fers a `'1 into register stage 39 of register 31 only when -c equals 1 andd equals 0 (i.e. d). Thus, thecol- It will be noted that the logical network providing this f ultimate collapse of the register comprises only two coincidence gates, namely, gates 36 and37, and inasmuch `as in the absence of the `desired ultimate collapse register stage 38 would normally contain a 0, any 1 which 4:is inserted into the said register `stage 38 cannot `possibly bepropagated further.

It should further be noted, of course, that the logical circuit shown in Figure 2 would normally include a parallel adder, and would in addition include gating and cloc'kdneans, similar to `gates 7a-'7d, 18a-8g land 9a-9g` of Figure l, for transferring signals from input register 30 4to intermediate registers 31, 32 and 33, land for thereafter transferring signals out of the said intermediate storage `registers into the said parallel adder. For purdiscussed in reference vto Figure v1. Moreover, fa's has already been discussed, this logical combining circuit comprising two gates may `be utilized in eifecting ultimate register collapse in any binary squaring circuit adapted to provide `the square of any even digit number.

While the foregoing discussion with respect to Figure 2 has utilized letter representations, an example of the actual pulses which would occur in various portions of the system of Figure 2 will now be given to facilitate an understanding of the actual squaring process. For purposes of example, .an arbitrary number 53, the square of which is 2809, may be-representedas follows:

A somewhat more complex situation occurs when the input number to be squared has an odd number of digits, and the logical combining circuit as Well as the overall squaring arrangement for one such odd input number condition is illustrated in Figure 3. Before proceeding with a detailed discussion of the circuit shown in Figure 3, however, it will again be convenient and helpful Ato ,ex-amine the factor disposition which occurs during :the squaring of an arbitrary number.

As has been discussed previously, the square of an arbitrary number, this time having an odd number of digits (e.g. seven), may be represented as follows;

The square of such a seven-digit number may, Aas before, be taken by adding the squares ofthe individual digits yto 'twice the cross products of the several digits, and the poses of simplicity, these latter velements have not been illustrated in Figure 2. AIn operation, the signals yin registers 31 and 32 would first -he Iadded in a rst parallel addition, and the digits in register 33 would thereafter be added to the sum of `this iirst parallel addition where- "by the final desired binary square is achieved in two lparallel additions. @the 'binary square of anNdigit number, where 'N equals 6, has been achieved through the utilization of As :has been discussed, therefore,

parallel additions (i.e. 'two parallel additions).

. The logical combining circuit comprising gates 36 land plicity, over the gate and half adder conguration already interconnected as shown, is preferred, due to its simfactors produced during such a squaring technique can vbe represented in accordance with their various powers, by a table as follows:

212 2li 210 20 2E 21 20 25 24 23 `22 2l. 2U

a o b o Vc o d o `e n f o g ab ac a ag af fly bg c!! dy 60 f 0 0 0 0 bc bd be 0f cf df ef 0 0 0 0 lcd ce Yde t It will be noted that in presenting the immediately preceding table (7), partial collapse of the register has been taken into account, but that three extra factors, namely, cd, ce and rde, appear respectively in the 28, 2rl and 2*? orders of the overall registers. This particular characteristic in fact arises whenever 'an odd digit binary number is factored `during asquaring process; and in each such case of an odd number, three extra factors will appear, as opposed to the one extra factor which appears during the squaring of an even numbered digit. The several factors cd, cc and de, can again be logically combined with other factors to produce an 'ultimate `collapse of the table into a minimum number of intermediate storage registers, and this collapse can occur 'as follows:

AExamining first the 2 and 28 columns, the factors d and de and the factors c land `cd in leach of these columns can be combined with one another, precisely in accord with the logical combining already discussed in reference to Figure 2. In particular, the factors d and de in the 28 column can be vlogically combined by inserting the factor d; in the 26 order of the rst register, and by placing the factor de in the normally 0 stage of the first register in the 2FI order. Similarly, the factors c and odin the p 2s 'order can be logically combined by inserting the factors f Il the rst register. This initial collapse can therefore be representedwith respect tothe 29, 28, 27 and 26 orders `of the several registers, as follows:

When so collapsed initially, it will be noted that the only order which now has an extra digit is the 27 order, and this particular order can be further collapsed by logically combining the factors de and ce; In particular, and referring to the said factors de and ce, the following truth table can be set up:

Referring now to the truth table (9) given immediately above, it will be noted that in combining the factors de and ce, the only times thatv a sum of binary l is placed in the 27 stage of the iirst intermediate storage register corresponds to cases 4 and 6. These two cases can be represented logically as gde and as coe (i.e., a binary l will be placed in the 27 order only when the relative states of the binary digits cde are 011 or 101), and for all other cases, a sum of is inserted in the said 27 order. Moreover, referring to lthe truth table (9), it will be noted that the only time a carry of l can possibly occur lis in case 5, and this particular case can be represented logically as cde (i.e. before a carry of l can possibly be transferred from the 27 order to the 28 order, each of the digits c, d, and e must be a binary 1). Accordingly, the linal collapse of the register with respect to the 29, 28, 27, and 26 orders thereof can be represented as follows:

cd cd or ede cile or ede d? ae af at] by bd be l bf cf A logical circuit adapted to provide the square of a seven-digit number and including means electrically proyviding the above discussed register collapse is illustrated tin Figure 3. In particular, it will be noted that, as was the case in the arrangements of Figures 1 and 2, the binary 'squaring circuit comprises an input register 40 and a vplurality of intermediate storage registers 41, 4Z and 43 in combination with a parallel adder 44. A gating chain comprising gates GS through G18 is disposed between input register 40 and intermediate storage register 42;

alud a fur-ther gating chain, comprising gates G19 through vG25, is disposed between the input register A40 and intermediate storage register 43. As before, the several digits acting as gate inputs, as well as the several factors of the squaring process, are designated lin Figure 3 at appro- .priate locations to facilitate an understanding of the gatarrangement.

12 The register collapse, discussed previously, may be accomplished through the utilization of a logical network comprising gates G1 through G7 and buffers B1 and B2; and the interconnections of these several components, as well as the logical signals appearingat various points in the combining circuit, are illustrated in Figure 3. Gate G7 has a pair of inputs, one of which is coupled to the l output terminal of register stage d in register 40, and the other of which is coupled to the 0 output terminal of register stage e in the said register 40, whereby a l output occurs from gate G7 only when d -is a 1 and e is a 0. This factor deis represented in stage 48 of register 41, and corresponds to the collapsed notation already discussed. Gate G3 has two inputs coupled respectively to the 1 output terminals of the cvand d stages in register 40 whereby the output of gate G3 is a binary l only when c and d are both 1, and this factor, represented as cd, is inserted into stage 45 of register 41, again in accordance with the previous discussion. Gates G1 through G6, in combination with buiers B1 and B2, provide the desired logical inputs to register stages 46 and 47 in register 41, and the logical arrangement will in fact become readily apparent by considering the pulse state notations disposed adjacent the input and output of each of these gates and buffers. The output of gate G6 feeds register stage 46 whereby a l is inserted in the said stage 46 only for the pulse conditions cde or cde. Similarly, the output of buier B2 feeds register stage 47 whereby a 1 is insert ed in the said stage 47 only for the pulse conditions cd or cde. Again, these relationships with respect to the stages 46 and 47 correspond to the logical collapsing of the register network already discussed.

As has been discussed previously, the logical circuit comprising gates G1 through G7 in combination with bulers B1 and B2, effects the desired collapse of three factors, and inasmuch as three such factors occur during a squaring of any odd digit number, the particular logical circuit shown in Figure 3 may be utilized without further complication in a network adapted to provide the square of any odd digit number. y

It will be appreciated, as before, that further gates and clock pulse sources, similar to gates 7a7d, 8a-8g and 9a-9g of Figure 1 should be provided to eifect transfer of pulses from register 40 simultaneously into intermediate storage registers 41, 42 and 43, and that still another transfer network should be provided for effecting paral- -lel outputs in sequence from intermediate storage registers 41, 42 and 43 to the parallel adder 44 which may be of the type mentioned vin the description of Figure 1V. The collapsed representation shown in Figure 3 again effects the squaring of a binary number with a minimum number of intermediate storage steps, and with a minimum number of parallel additions; and inthe particular case of the seven-digit input number, the squaring is accomplished through utilization of three intermediate storage registers and two parallel additions. Y

By way of example, the pulse states in various portions of the circuit for an arbitrary input train, again chosen to represent the aforementioned number 53, can be represented as follows, and it will be appreciated that the designated sum appears at the output of the parallel adder shown in Figure 3: l

While the foregoing discussion has thus been concerned with preferred embodiments in accordance with the present invention, many variations will be suggested to those skilled in the art. In particular, it will be noted registers are ernplo'yed,` a further important part `of the invention has resided in logically combining various facthat when register arrangements are employed, various register stages normally have "s therein regardless of the binary number beingrsquared. If desired, these zerotion of powers of numbers having other bases, such as containing registerstages may be utilized to effect a reternary numbers. By way of example, a technique will location of the actual` stages which contain certain facnow be described for producing a circuit capable of detors, if such relocation is dictated by other considerations. riving a binary cube, and it will be appreciated that the Moreover, Vitwill be appreciated that the use of intermedifollowing discussion employs the same techniques and ate st'orager'egisters is highly desirable due to the simconsiderations already utilized in producing circuits caplicity of the gating networks which can be employed pable of deriving binary squares. It will further be noted 4for transferring signals from an input register, or from a 10 from the following discussion, that by somewhat more plurality of input lines, into the said storage registers aud refined treatment of the several gating means employed, thereafter into a parallel adderl However, other logical a further Veffect of collapsing the addition fields is expe- DCWOIkS, ill CGmbIl-OLU With 'aPPIOPIiaCiY timed conrienced beyond the mere superimposition of factors, altrol sources can be employed for transferring digits diready described, rectly out of therinpt register into an accumulator. Thus, employing the method by which the squaring FOI instantie, referring' ii0 Figi-1re i and adopting the devices of the present invention were previously exalternate collapsing scheme already discussed in reference p1ained, let us rst consider the quantity (ABCD) as a i0 Figlls 2 and 3, the digits dbf-d can be gated Oui 0f binary field. This is effectively the sum of the comthe input register to the parallel adder as a first parallel ponents, ,as in A+B+C+D- NOW the Cube of this quantrain a, bc, b2, 0, c, 0, d; and after this rst train has tity is made uplof the sum of the cubes of the cornbeen so gated into the parallel adder, the gating network ponents, three times the products of permuted squares may thereafter gate a second train out of the said input and single factors, and six times the products of perregister, represented as ab, ac, ad, bd, cd, 0, O. This sucmuted single factors taking three at a time. Employcessive transfer of parallel trains is in accord with the` p ing the technique already described, the following table logical factors comprising the binary square already dis` 25 can be set up to illustrate `the factoring process:

same V'.vonsiderations apply directly in the derivation of any binary power, and for that matter apply to the derivacussed, and a similar `consideration applies, of course, It should be noted that the quantities in table (l1) have to each of the other embodiments of the present in- 40 not been collapsed into their respective closed posivention. tions, and in fact these quantities may be rewritten in a The foregoing discussion has, of course, been primarily more elementary form. In binary notation, the squares concerned with techniques and structures adapted to efand cubes of a bit are merely the bits themselves, so fect circuits capable of deriving the binary square of a, the powers may be disregarded. Further, amultiplication binary number more simply and with fewer additions by three may be accommodated by so duplicating the than hasnbeen the case heretofore. The essence `of the present invention, as thus described, resides primarily in column, and the ,doublef factor is the same notation the provision of gating arrangements adapted to gate one column tothe left. Also the factor of `6 may be proper factors of the power-taking process to appropriate ,p reduced Yby shifting the bit notation one to the left, where orders of a parallel adder at appropriate times; and in it becomes a factor of 3, and proceeding therefrom as those forms of the invention wherein intermediate storage just described. Under this treatment, table (1l) may be rewritten as follows:

21o 2n 2s 21 2o 2r 2t 2a 21 21 2n A B AB AB AC AO AO AO AD AD BO BD The cube might be effected now by gating: the input `bits to appropriate register stages corresponding to table (1,2), as described, and adding directly. However, tbenumber of additions required can be reduced appreciably by collapsing each column upward. The next step accordingly are required, becomes one of logicalcollapsing, somewhat akin to the While the preceding discussion has, as mentioned, been technique already described, in which single items were concerned with the derivation of a binary square, these t .75 cut down in squatting-devices.

tors with one another thereby to` logically 'collapse the intermediate register stagesto a desired minimum num-V ber of stages, thereby to decrease the number of register stages as well as the number Vof parallel additions which quantity that the single factor is the bit notation in oneV It may be noticed that the elds tobe'collapsed lie -to the left of the column headed 23. Let us first consider column24,whichis: 'Y

AD BC BD CD BCD or ve separate items, and this may in fact readily be compressed to a total of two items. The factors BC and BD may, of course, be expressed in two columns as:

BED BCD (BCD where the factors with the barred items are included in one bit position. Also notice that the original BCD item in the 24 column may be included in this position as well. vNow, AD and CD may be similarly compressed so that the whole expression may be expressed, using two col- -umns (namely the 24 and 25 columns), as:

BED BCD BCD Y ACD D Y AO (ACD BOD Thebarred factors in table (13) are, ofcourse, binary.. `zeros, and by reason of this collapse, gating may effect in two registers what was formerly contained in five.

Now, the next column to the left (column 25) must i have BCD and ACD in addition to its other factors so that it appears as: v

BCD ACD AC BD ACD ACD BCD But, since there is a doubling of factors here, this in turn may be expressed in two columns (namely the 25 g and 26 columns), as:

BCD VACD AC BD y with again a reduction to only two registers. ow, the

, 2 column, including the cast-olf BCD and ACD roftable (14) is: Y Y l BCD ACD ACY ABD ACD Note here thatl ACDV appears twice; moreovenAC and AD may be expressed (see the development'of table (13) above) as:r Y

ACD

ACD

(AED

and Va combining of BCDvand ABD results 'in the` fae- Vtorsz" Y A'BCD ABCD (ABD The total collapsing operation thus results in a compression of the 28 column, into the 28 and 2'I columns, as follows:

AED- CD A (ACD ABCD CD AB (ABCD whereby the seven input factors have reduced to three.

Continuing the process, the 2'1 column, with all the carries shown in table (1(5),v becomes: l

AACD

ACD ABCD AB AC AD ABD ABC BC or a total of nine factors. Note again that the factor ACD can be shifted-Ato the next, or 28, column over as a duplicating factor.

Another ACD carry emerges from the combining of AC and AD, as vhas already been described, whereby these factors become:

the 2I column, and four carries are placed in the 2' column.

-In the same manner, the whole ofcolumn 2, with carries, now becomes: Y. l

ACV ABC ACD ACD ABC ABCD essere@ i7 which; with the-duplicationof ACD land ABC collapses at once to:

ACD ABC AC ABCD in the 28 and 29 columns. Column29-can easily accom-l modate these carries, so' that thesaid 29 column now appears as:

A ACD ABC The completed cube logicicontained in three registers is, therefore:

rs withthese@` intermediate register stages, .would appear as follows Register one- 01100101011 Register two 00000000000 Register three 01000001000 Binary sum` 10100110011 2m 2u 2s 21 i 2er 2a 24 2ay 2z 2x 2u ABQD aegon@ AB A` Ao ABCD B Ao e BD eD D U ABCD t ACD/ y '-2' y i BED i `Ano ABCD i `Reg'rwo n" ABC -130D (ABE). (AB-6D BD (ggg) BD o o o [6D AED Y o o AD o o o Reg Three ACD 0 (ACD) (ACD) Table- (.17)1abovet represents directlyitheugating `technique f as `well as.A the t register: stages'l for three, registers which `may be employed in deriving thebinary cubefof a number ABCD.` An overallficircuit constructed bin` acrcordance with the logic :of table( 17) may, asbeforeand in 1a manner similar to the circuits of Figures `1, Zand 3, comprise: an input register adaptedto: receive the` individual factorsA, Bf C, and D; gating` means adapted to simultaneously transfer these factorsrfromtvthe*` input register into the appropriate'stages. ofthe" three` registers designated in table (17); anda paralleladderladapn ed to thereafter sumy the factors in thersaidlthreeuregisterslin a` total of two successive` parallel additions:v

Various gating networks willwbefsuggestedl to` those skilled in the-art for transferring digits from anfinput reg ister` so that they appear as proper factors inappro priate stages ofthe intermediateregister.l By way `ofertample, itshould b`e` noted that the gating network: .for transferring digits-fromtheV Ag'. C andy DJpositions ofthe input register to' the 214 stagezofA` the rstiintermediate register, should befadaptedi tortransfer al inta-the said 24 `stage whenthe-A, C and D digits are respectively 011 or 101. Similarly; the' gating networkwhichiamust be employed for `transferring i digits from the` A1,. B25 `C and D positionsrof therinput register to thel 27stage1of=`lthe first intermediate storage.` register shouldlibefssuchithat a 1 is placed in the said-27 stagecof the rstfintermedite storage register*whenl'thelinput digits AsBLf C `andJD are respectively 1111,` 1101 orf1110L1 The'4 requirements `of the other portions of.` this gating'networklwill similarly be readily apparent from `arr examinationro'ff'table1(17); and in fact-the table (17) maybe lconsideredi to repre` sent directly the circuit `of al binary' cubingtsystem expressed in mathematical terminology'.

As mentioned previously, thefseveralfactors: inf. the register stages, indicated in tablef (17 mustbei summed in two parallel additions to effect the ultimate binary cube of the input number; By way of example,A let us consider that the` inputnumber ABCD-'is represented as 1011 (namely, decimal number 11), and thatthisnuma ber istof be cubed; The actual signals Whichfwouldfappearin thevarious registerstages `of tabletv (17), `andlat the output of the binaryadder employedin conjunction when. N is Van even number and N -1 K- 2J when N` is an odd. number, `first means forI transferring signals representative of selected single ones of saidN digits from said input means to selected ones of the stages 5'() in` saidK storage registers, second means for transferf ring signals representative of the logical combination of selected `pairs of said- N Ydigits from Vsaid inputmeans tofother selected ones ofthe stages in said K storage registers, third means for transferring signals represen.-

tative of the relative states of preselected ones of said N digits to still other ones of the stages in said K storage registers, and adder means operative subsequent to operation of said rst, second, and third meansfor summing the signals in the said K storage registers in a'total of K-l parallel additions.

2. The combination of claim 1 wherein said input means comprises an input register.

3. The combination of claim-2 wherein each ofsaid rstgtlsecond, and third transferringI means includes gating-means.

4. The combination of Vclaim 2 wherein said second transferring means comprises a. plurality of .coincidence gates, each of saidr'gates having pairsiofinputs coupled respectively. to the outputsof different pairs of stages in: saidinput register.

5.` yIn ar'logical binarypoweringcircuit, an input means for-lsettingr-fupl a plural-digit binary number to be pow'- ered,.` accumulator means having a plurality of different orders respectively independent of one another, iirstkgating.'` means `forLtr-ansferringiirst signals Arepresentativevof l@ dilferent individual digits of said plural-digit binary number to iirst selected orders of said accumulator. means,

' second gating means for transferring second signals representative of the logical combinations of dilerent pairs of Said plural digits to second selected orders of s-aid accumulator means, and third gating means for transferring third signals representative of the comparative digit states of a logically combined preselected pair of said digits and of a preselected single digit in said pluraldigit number to third selected orders of said accumulator means, whereby the output of said accumulator means comprises a binary number representative of the square of said input plural-digit binary number.

6. The combination of claim wherein said pluraldigit binary number has an odd number of digits, said third means including means responsive to the comparative digit states of different preselected pairs of said plural-digit number.

7. The combination of claim 5 wherein said input means comprises a plural-stage input storage register.

input lines to said accumulator means, second gating means responsive to the relative signal stateskof digits on different ones of said input ilines for transferring a plurality of independentsecond signals, representative respectively of the logical combinations of different pluralities ofsaid, digits, from said input Ilines to ,saidy accumulatormeans, said accumulator means .being operative to sum said tirst and second signals whereby the output of said accumulator means comprises the power of said multi-digit number.

15. The combination of claim 14 wherein said input lines comprise the outputs of a plural-stage input register.

16. The combination of claim 15 wherein said accumulator means comprises a plurality of intermediate storage registers, and a parallel adder coupled to the outputs of said intermediate storage registers.

17. In a logical powering circuit, a plural-stage input .register adapted to receive input` signals representative of 8. The combination of claim 7 wherein said first, second and third transferring means include coincidence gating means.

9. The combination of claim 8 wherein said accumulator means comprises a plurality of intermediate storage registers having a plurality of storage stages independent of one another, the inputs of said plural stages being coupled respectively to outputs of said input stor- -age register Via.- said coincidence gating means, and a parallel adder having inputs thereof coupled to the output of said intermediate storage registers.

10. In a logical binaryV powering circuit, an input register, means coupling -a binary number to said input register, a plurality of intermediate storage registers, first means transferring a plurality of rst signals from said input register to a preselected plurality of different stages of said intermediate storage registers respectively, said rst signals being representative respectively of different preselected individual digits of said binary number, second means transferring a plurality of second signals from said input register to another preselected plurality of different stages of said intermediate storage registers respectively, said second signals being repre- Sentative respectively of the Ylogical combination of different pluralities of digits comprising said binary number, and adder means for adding together the digit-representing signals in different ones of said plurality of intermediate storage registers.

11. The combination of claim 10 wherein said rst and second means comprise simultaneously operative gating means.

12. The combination of claim 10 wherein said binary number comprises N digits, said plurality of intermediate storage registers being K in number, where when N is an even number, and

. Yferent selected individual ones of said digits from Said the digits of a number to be powered, a plurality of plural-stage intermediate storage registers, gating means for transferring said input signals from said input register to rst preselected stages of said intermediate storage registers, said gating means including means responsive to the comparative signal states of digits in preselected diiferent stages of said input register for transferring further signals to second preselected stages of said intermediate storage registers representative respectively of diiferent logical combinations of the signals in Vsaid pre-- selected different stages of said input register, and means for adding the signals in said intermediate storage registers in parallel.

l 18. In a logical binary powering circuit, an input means for setting up a plural-digit binary number to be powered, said input means comprising a plural stage storage register each stage of which has a 1 output terminal and a 0 output terminal, accumulator means having a plurality of different orders, rst means for transferring first signals representative of different digits of said plural-digit binary number to different selected orders of said accumulator means, second means for transferring second signals representative of the logical combinations of different pairs of said plural digits to dilerent selected orders of said accumulator means, and third means for transferring third signals representative of the comparative digit states of a logically combined preselected pair of said digits and of a preselected single digit in said plural-digit num- -ber to different selected orders of said accumulator means, whereby the outputof said accumulator means comprises a binary number representative of the square of said input plural-digit binary number, said third transferring means including first and second coincidence gates, means respectively coupling the inputs of said rst coincidence gate to the l output terminals of a preselected pair of stages in said plural stage storage register, means respectively coupling the inputs of said second coincidence gate to the 1 output terminal of one of said preselected pair of stages, and to the 0 output terminal of the other of said preselected pair of stages, and means coupling the outputs of said irst and second gates to preselected adjacent orders in said accumulator means.

19. In a logical binary powering circuit, input means for setting up a plural-digit binary number to be powered, rst and second plural stage storage registers, first means for transferring rst signals representative respectively of individual ones of said plural digits to dilferent spaced stages of said rst register, second means for transferring second signals representative respectively of logical combinations of different pairs of said plural digits to different selected stages of said second register, third means for transferring a third signal representative of the relative `states of preselected ones of said plural digits to a stage of said rst register located between selected ones of said spaced stages,- and adder means operative subsequent to operation of said rst, second, and third transferring means for summing the signals in said rst register in parallel with the signals in said second register.

20. The combination of claim 19 including clock means for causing said first, second and third transferring means to operate simultaneous with one another.

21. In a logical binary powering circuit, input means for setting up a plural-digit binary number to be powered, means responsive to selected ones less than all of said plural digits for producing first signals representative respectively of said selected digits, means responsive to the remaining ones of said plural digits for producing second signals representative of the comparative states `of said remaining digits and of others of said plural digits,

means responsive to said plural digits for producing third signals representative respectively of logical combinations of selected pluralities of said plural digits, register means, first gating means for simultaneously transferring said rst, second and third signals to different preselected stages of said register means respectively, adder means, and second gating means operative subsequent to said first gating means for transferring said rst, second, and third signals from said register means to said adder means wherein said signals are summed in accordance with their relative positions in said register means.

22. In a logical powering circuit, a plurality K of plural stage storage registers, the successive stages of each of said registers being representative respectively of successive mathematical powers to a preselected base, each of said registers having mathematical power-repred senting stages corresponding `to stages representing like mathematical powers in others of said registers, input means providing an N digit number to be powered, gating means responsive to the several digits of said N digit number for transferring signals, representative of the coefficients of a mathematical powering expansion of said N digit number, to the several power-representing stages of said plural registers in accordance with the several powers of said expansion, at least one power-representing stage in at least one of said registers normally having no signal transferred thereto by said gating means, logical means responsive to the relative states of a preselected plurality of said N digits for transferring an auxiliary signal representative of said relative states to said one stage whereby all the factors of said mathematical eX- pansion are stored in the several stages of said K registers, where when N is an even number and when N is an odd number, and means operative subsequent to operation of said gating and logical means for summing the signals stored in said K registers to produce an output signal representative of the desired power of said N digit number.

References Cited in the le of this patent UNITED STATES PATENTS 2,404,047 Flory et al. July 16, 1946 2,764,343 Diener Sept. 25, 1956 OTHER REFERENCES Richards: Arithmetic Operations in Digital Computers, D. Van Nostrand Co., Inc., Princeton, New Jersey; copyright February, 1955, pages 138 to 140.

UNITED STATES PATENT OFFICE Certificate of Correction Patent N o. 2,890,829 June 16, 1959 J Robert Logan It is hereby certified that error appears in the printed specification of the above numbered patent requiring correction and that the lsaid Letters Patent should read as corrected below.

Co1umn 9, line 20, after intermediate insert -storage; line 31, for (i.e. d) read -(i.e. d)-; column l0, line 73, for factors read. factor-5 column l5, line 46, strike out ACD.

Signed and sealed this 1st day of March 1960.

Attest: KARL H. AXLINE, ROBERT C. IWATSON, Atestz'ng Oycer. 'ormm'saoner of Patents. 

